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1 power factor correction controllers isl6730a, isl6730b, isl6730c, ISL6730D the isl6730a, isl6730b, isl6730c, ISL6730D are active power factor correction (pfc) controller ics that use a boost topology. (isl6730b, isl6730c, ISL6730D are coming soon.) the controllers are suitable for ac/dc power systems, up to 2kw and over the universal line input. the isl6730a, isl6730b, isl6730c, ISL6730D are operated in continuous current mode. accurate input current shaping is achieved with a current error amplifier. a patent pending breakthrough negative capacita nce technology minimizes zero crossing distortion and reduces the magnetic components size. the small external components result in a low cost design without sacrificing performance. the internally clamped 12.5v gate driver delivers 1.5a peak current to the external power mosfet. the isl6730a, isl6730b, isl6730c, ISL6730D provide a highly reliable system that is fully protected. protection features include cycle-by-cycle overcurrent, over power limit, over-temperature, input brownout, output overvoltage and undervoltage protection. the isl6730a, isl6730b provide excellent power efficiency and transitions into a power saving skip mode during light load conditions, thus improving efficiency automatically. the isl6730a, isl6730b, isl6730c, ISL6730D can be shut down by pulling the fb pin below 0.5v or grounding the bo pin. the isl6730c, ISL6730D have no skip mode. two switching frequency option s are provided. the isl6730b, ISL6730D switch at 62khz, and the isl6730a, isl6730c switch at 124khz. features ? reduce component size requirements - enables smaller, thinner ac/dc adapters - choke and cap size can be reduced by 66% - lower cost of materials ? excellent power factor over line and load regulation - internal current compensation - ccm mode with patent pending ip for smaller emi filter ?better light load efficiency - automatic pulse skipping - programmable or automatic shutdown ? high reliable design - cycle-by-cycle current limit - input average power limit - ovp and otp protection - input brownout protection ? small 10 ld msop package applications ? desktop computer ac/dc adaptor ? laptop computer ac/dc adaptor ?tv ac/dc power supply ?ac/dc brick converters figure 1. typical application figure 2. pfc efficiency + isl6730 vcc isen icomp vin gate gnd fb bo vreg comp v line v out v i output power (w) efficiency (%) isl6730c isl6730a, skip 100 95 60 65 70 90 85 80 75 0 20 40 60 80 100 table 1. key differences in family of isl6730 version isl6730a isl6730b isl6730c ISL6730D switching frequency 124khz 62khz 124khz 62khz skip mode yes-fixed yes-fixed no no february 26, 2013 fn8258.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 2 fn8258.0 february 26, 2013 pin configuration isl6730a, isl6730b, isl6730c, ISL6730D (10 ld msop) top view 7 8 10 9 4 3 2 1 gnd isen icomp vin gate vreg fb vcc 6 5 bo comp pin descriptions pin # i/o symbol description 1 - gnd ground pin. all voltage levels refer to this pin. 2 i isen current sense pin. the current through this pin is proportional to the inductor current. 3 i/o icomp current error amplifier output pin. 4 i vin input voltage sense. this pin provides the reference voltag e to shape inductor current. connect this pin to a resistor div ider from the rectified input voltage. the resistor divider ratio is used to adjust the phase lag between input voltage and the input cur rent. the phase lag is required to compensate th e phase lead generated by the emi filter. 5 i/o bo this pin should be decoupled to gnd with a minimum 0.1f ceramic capacitor. the bo pin is a voltage follower, which will follow the dc voltage of the vin pin. the bo pin is internally tied to gnd through a resistor r is . the decoupling capacitor provides ripple filtering. when the voltage at the bo pin (v bo ) drops below brownout voltage threshold, the controller enters shutdown mode and the gate drive is disabled. the bo pin will be disa bled when the fb pin drops below the enabling threshold. 6 i/o comp output of the error amplifier. the voltage of the comp pin sets the input power. during start-up, a small charge curren t will slowly ramp up the voltage of the comp pin. 7 i fb voltage feed back pin. connect this pin to a resistor divide r from the output. the resistor divider sets the output voltage . when the fb pin voltage exceeds 104% of the reference voltage, overvo ltage-protection is triggered and gate drive is disabled. when the fb pin is below 10%, the device is put into shutdown mode . there is an internal pull-down current source for open loop protection. 8 - vreg output of internal regulator. the voltage having a 2% tole rance over line, load and operating temperature. bypass to gnd with a 47nf low esr capacitor. vreg can source up to 10ma. this pin is not recommended for usage other than bypass. 9 i vcc power supply pin. the vcc pin should be decoup led to gnd with a minimum 0.1f ceramic capacitor. 10 o gate push-pull gate drive for the external mosfet. output voltag e is clamped at 12.5v. this pin provides typically 2a sink an d 1.5a source capability. ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6730afuz 6730a -40 to +125 10 ld msop m10.118 isl6730bfuz ( coming soon ) 6730b -40 to +125 10 ld msop m10.118 isl6730cfuz ( coming soon ) 6730c -40 to +125 10 ld msop m10.118 ISL6730Dfuz ( coming soon ) 6730d -40 to +125 10 ld msop m10.118 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6730a . for more information on msl please see techbrief tb363 . http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, isl6730c, ISL6730D 3 fn8258.0 february 26, 2013 block diagram fb comp gate pwm vcc control logic vin isen oscillator comp gnd otp vcc bo i fb r sen r is = 16k ? icomp i ref ceq gen. current mirror over power limit soft-start enable 2.5v skip 20a skip clamp skip 2:1 0.25 vin bo 2 ----------------------------- c o m p b q 1 c out v out l comp-1v r cs v cs r is i isen 2 ---------------------------------- - = c f1 c f2 v line c f3 emi choke uvlo r fb1 r fb2 l m r in2 c bo r in1 d i cs i oc 2 ------------- - > i cs compb d f1 d f2 c reg linear regulator vreg v i gmi gmv http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, isl6730c, ISL6730D 4 fn8258.0 february 26, 2013 application schematics typical 300w application schematic r5 0.068 220n c8 c6 470p c12 100p 2m r1 2m r3 4.02k r14 c10 18n c11 1.2n tp6 cr12 47n dz1 3.3v 2 1 l1 100u s1m-13-f d7 c2 100n s1m-13-f d8 l2 0.6m q1 ipa60r600c6 1 3 2 c5 470p s3kb-tp d4 40k r19 c4 470n r13 65k vcc s3kb-tp d6 c3 470n r4 51k 2.2 r2 l3 4 3 2 1 270u c1 1 2 r18 82.5k s3kb-tp d5 d2 c3d04060e 3 1 2 s3kb-tp d3 f1 r9 3.16k 4.3m r11 4.3m r8 3.3m r6 3.3m r10 1.5k r17 vcc pe ac2 ac1 c13 220p p1 p4 p5 p2 p3 p7 tp3 tp5 tp4 s3kb-tp d1 tp2 tp1 tp9 tp10 gnd dc+ 1u c9 p6 u1 isl6730b fb 7 gate 10 gnd 1 isen 2 icomp 3 vin 4 bo 5 6 comp reg 8 vcc 9 390v 85~265vac c14 470n c18 1.5u c15 100n c16 1n http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, isl6730c, ISL6730D 5 fn8258.0 february 26, 2013 typical 85w application schematic application schematics (continued) r5 0.22 220n c8 c6 470p c12 100p 2m r1 2m r3 6.2k r14 c10 68n c11 470p tp6 cr12 47n dz1 3.3v 2 1 l1 128u s1m-13-f d7 c2 100n s1m-13-f d8 l2 2.2m q1 ipa60r600c6 1 3 2 c5 470p s3kb-tp d4 40k r19 c4 330n r13 65k vcc s3kb-tp d6 c3 220n r4 51k 2.2 r2 7.5m l3 4 3 2 1 56u c1 1 2 r18 68k s3kb-tp d5 d2 c3d04060e 3 1 2 s3kb-tp d3 f1 r9 2.1k 4.3m r11 4.3m r8 3.3m r6 3.3m r10 1.5k r17 r15 dnp r16 dnp 10k r20 pfc_en vcc pe ac2 ac1 470n c7 c17 1n c13 220p p1 p4 p5 p2 p3 p7 tp3 p8 p9 tp5 tp4 s3kb-tp d1 tp2 tp1 tp9 tp10 gnd dc+ u1 isl6730a fb 7 gate 10 gnd 1 isen 2 icomp 3 vin 4 bo 5 6 comp reg 8 vcc 9 1u c9 p6 390v 85~265vac c14 470n c18 2.2u c15 100n 2n7002 q2 1 2 3 c16 1n http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 6 fn8258.0 february 26, 2013 absolute maximum rating s thermal information vcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v gate to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +18v vin, bo, isen, fb and comp to gnd. . . . . . . . . . . . . . . . . . . . . . . .-0.3v to +6.3v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd-c101e. . . . . . . . . . . . . . . . . 1kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma recommended operating conditions vcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v to + 20v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical) ja (c/w) jc (c/w) msop package (notes 4, 5) . . . . . . . . . . . . 137 39 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the "case temp" location is taken at the package top center. electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c . parameter symbol test conditions min (note 8) typ max (note 8) units v cc supply current start up current i start v fb = 1v, v cc < v cc (on) 73 106 139 a standby current i stdn v fb = gnd, v cc > v cc (on) 179 237 295 a skip mode current i ccskip v fb = 2.5v, comp = skip*0.25 +1v 580 690 800 a operating current (note 6) i cc gate is floating 3.2 3.7 4.2 a vcc uvlo uvlo rising threshold v cc(on) 91011v uvlo falling threshold v cc(off) 6.7 7.5 8.3 v uvlo threshold hysteresis v cc(hys) -2.5- v regulator voltage vreg overall accuracy i ref = 0 to -10ma, v cc = 15v, load capacitor = 47nf 5.16 5.4 5.6 v current limit 30 50 70 ma pwm converters minimum duty cycle, isl6730a f sw = 124khz - 2.57 4.66 % maximum duty cycle, isl6730a f sw = 124khz 94.8 96.5 - % oscillator free running frequency, isl6730a t a = -40c to +125c, v in = 0.6v 98 107 116 khz free running frequency, isl6730a t a = -40c to +125c, v in = 2.5v 114 125 136 khz pwm ramp amplitude v m 1.33 1.46 1.59 v gate driver gate drive pull-down resistance v cc = 15v, i gate = 15ma - 2.33 4.46 ? gate drive pull-up voltage drop v cc = 9v, i gate = 15ma 0.15 0.3 0.45 v gate drive max. sourcing/sinking current -1.5- a http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 7 fn8258.0 february 26, 2013 rise time c o = 2.2nf, v cc = 15v, gate voltage rise time from 10% to 90% of v gc -3462ns fall time c o = 2.2nf, v cc = 15v, gate voltage fall time from 10% to 90% of v gc -3457ns gate clamp voltage v gc 11 12 13 v voltage reference reference voltage vref 2.48 2.5 2.52 v feedback pin pull-down current i fb -65-na rising threshold to enable converter fb_en 280 300 320 mv falling threshold to disable converter fb_dis 190 202 214 mv enable hysteresis fb_hys - 100 - mv voltage error amplifier dc gain -92-db error amp transconductance gmv 50 77 104 a/v isource/sink -13-a comp offset voltage v comp_off 0.95 1.01 1.07 v comp soft-start enable voltage v comp_en 0.58 0.64 0.75 v input voltage sensing vin leakage current -9-na multiplier gain gmul comp = 2.5v, v in = 1.0v, bo = 1.0v, i sen = 50a 0.196 0.25 0.296 v/v current error amplifier current dc gain a idc i icomp / i isen 1.6 1.9 2.2 a/a error amp transconductance gmi i icomp = 20a 205 268 331 a/v icomp source/sink current (note 7) -60-a current sensing input offset -3 2 7 mv light load efficiency enhancement and overpower protection skip mode comp threshold v scmt 1.32 1.36 1.4 v comp upper limit v cul 3.53 3.85 4.17 v comp valid range v cul -1v 2.5 2.83 3.16 v fb exit threshold voltage v fb_exit i isen = 0a 87 88 89 % isen exit threshold current i sen_exit v fb = 2.5v -38 -29 -20 a brownout detection brownout rising threshold v bo_r 478 494 510 mv brownout falling threshold v bo_f 387 401 415 v overvoltage protection overvoltage protection v ovp fraction of the set point; ~1s noise filter 102.9 104.1 105.3 v overcurrent protection overcurrent threshold i oc -197 -177 -159 a electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c . (continued) parameter symbol test conditions min (note 8) typ max (note 8) units http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 8 fn8258.0 february 26, 2013 thermal shutdown shutdown temperature (note 7) - 160 - c thermal shutdown hysteresis (note 7) -25-c notes: 6. this is the v cc current consumed when the device is active but not switching. does not include gate drive current. 7. limits should be considered typical and are not production tested. 8. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. electrical specifications operating conditions: v cc = 15v, t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c . (continued) parameter symbol test conditions min (note 8) typ max (note 8) units typical performance curves figure 3. feedback accuracy figure 4. f sw vs temperature, v cc = 15v figure 5. a idc vs temperature figure 6. f sw vs v in, t a = +25 c temperature (c) vfb normalized (%) 99.50 99.75 100.00 100.25 100.50 -40 -20 0 20 40 60 80 100 120 140 f sw normalized (%) 99.0 99.5 100.0 101.0 v in = 0.6v v in = 2.5v temperature (c) -40 -20 0 20 40 60 80 100 120 140 100.5 temperature (c) 97 98 99 100 101 -40 -20 0 20 40 60 80 100 120 140 a idc normalized (%) 75 80 85 90 95 100 105 f sw normalized (%) v in (v) 0 0.51.01.52.02.53.0 http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 9 fn8258.0 february 26, 2013 figure 7. uvlo thresholds vs temperature figure 8. v cc supply current vs temperature figure 9. gate driver ability vs temperature (load = 2.2nf) typical performance curves (continued) 98 99 100 101 102 -40 -20 0 20 40 60 80 100 120 140 up down hystersis temperature (c) uvlo threshold normalized (%) threshold threshold 98 99 100 101 102 -40 -20 0 20 40 60 80 100 120 140 i cc temperature (c) v cc current normalized (%) (gate floating) i start temperature (c) driver time normalized (%) 96 98 100 102 104 106 108 110 112 -40 -20 0 20 40 60 80 100 120 140 rise time fall time http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 10 fn8258.0 february 26, 2013 functional description vcc undervoltage lockout (uvlo) the isl6730a, isl6730b, isl6730c, ISL6730D start automatically once the voltage at vcc exceeds the uvlo threshold. shutdown when the vfb pin is below 0.2v, the controller is disabled and the pwm output driver is tri-stated. when disabled, the ic power will be reduced. during shutdown, the comp pin is discharged to gnd and the controller is disabled. the over-temperature protection (otp) is still alive to prevent the controller from starting up in a high te mperature ambient condition. in the event that the fb pin is disconnected from the feedback resistors, the fb pin is pulled to ground by an internal current source i fb . when the fb pin voltage drops below 0.2v, the gate driver is disabled. the isl6730a, isl6730b, isl6730c, ISL6730D enters shutdown mode. soft-start the comp pin is released once the soft-start operation begins. a 13a current sources out to the rc network connected from the comp pin until the fb pin voltage reaches 90% of the reference voltage. switching is inhibited when the comp pin voltage is below 1v. when the comp pin reaches 1v, the current error amplifier and the gate driver are activated and the converter starts switching. during uvlo, brownout and shutdo wn, the comp is pulled to the ground. input voltage sensing the vin pin is needed to sense the rectified input voltage. the sensed semi-sinusoidal waveform is needed to shape inductor current, which helps achieves unity power factor. at the same time, the voltage on the vin pin is used to generate the negative capacitive element at the input. th is will cancel the input filter capacitor, c f . canceling the effect of c f will increase the displacement power factor and alleviate the zero crossing distortion, which is related to the distortion power factor. the bo pin also utilizes the vi n resistor divider for voltage sensing. set the resistor divider ratio to satisfy the brownout requirement. first, calculate the resi stor divider ratio, k bo . where v f is the forward voltage drop of the bridge rectifier and the voltage drop of d f1; d f2 . then, select the r in2 based on the highest reasonable resistance value. then select the r in1 based upon the desirable minimum rms value of the line voltage for the pfc operation. inductor current sensing the current sensing of the converter has two purposes. one is to force the inductor current to track the input semi-sinusoidal waveform. the other purpose is for overcurrent protection. refer to figure 11 for the current sensing scheme. the sensed current i cs is in proportion to the inductor current, i l as described in equation 3. where: r cs is the current sensing resistor with low value in the return path to the bridge rectifier. r sen is the current scaling resist or connected between isen to the r cs . figure 10. input voltage sensing schematic bo r in1 c bo vin c f2 v line c f3 emi choke l m d f1 d f2 r in2 k bo v bormax v rmsmin 2v f ? ------------------------------------------- = (eq. 1) r in1 k bo 1k ? bo --------------------- r in2 ? = (eq. 2) i cs 1 2 -- - r cs r sen --------------- - i l ?? = (eq. 3) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 11 fn8258.0 february 26, 2013 a high value r cs renders more accurate current sensing. it is recommended to use the r cs to render 120mv peak voltage at the maximum line voltage during full load condition. where is the efficiency of the converter at the maximum line input with full load. since the r cs sees the average input current, high value r cs generates high power dissipation on the r cs . use a reasonable r cs according to the resistor power rating. the worst-case power dissipation occurs at the input low line when input current is at its maximum. power dissipation by the resistor is: where: i rmsmax is the maximum input rms current at the minimum input line voltage, v rmsmin . select the r sen according to the peak current limit requirement. the resistor is sized for an overload current 25% more than the peak inductor peak current. negative input capacitor generation (patent pending) the patent pending negative capacitor generation capability of the isl6730a, isl6730b, isl6730c, ISL6730D allows the capacitor c f2 to be moved from before the bridge rectifier (figure 12) to after the bridge rectifier (figure 13). thus, a smaller lower cost c f2 can be used. the change in topology reduces the size of the emi filter. furthermore, c f1 can be increased thus decreasing the size of l f (figure 13). for applications where the output power is above 500w, the negative capacitance helps to improve the power factor dramatically. please refer to table 2 for the recommended filtering capacitor to be placed after the bridge rectifier, c f1 . additional c f1 may be used to accommodate the use of small boost inductor or to eliminate the differential mode filter inductor as long as the equipment meets the power factor or goal. the equivalent negative capacitor is a function of the input voltage divider ratio, k bo , the current sensing gain and current compensation error integration gain. adjusting the negative ceq can be achieved by adjusting the current compensation network. frequency modulation the isl6730a, isl6730b, isl6730c, ISL6730D can further reduce emi filter size by lowering the differential noise power density. the reduction is achieved by switching frequency modulation. the frequency varies with the vin pin. the switching frequency reaches the peak value when the vin pin voltage is 2v as shown in figure 6. the peak value of isl6730a/c is 124khz, and the isl6730b/d is 62khz. output voltage regulation the output voltage is sensed through a resistor divider. the middle point of the resistor divider is fed to the fb pin. the resistor divider ratio sets the output voltage. the transconductance error amplifier generates a current in proportion to the difference between the fb pin and the 2.5v internal reference. the pfc is stabilized by the compensation network that is connected from the comp pin to the ground. the voltage of the comp sets the input average power by determining the amplitude of the current reference. to keep the figure 11. inductor current sensing scheme q1 cout vout l cf1 v i rcs isen rsen current mirror 2:1 i cs 0.5 i oc > i cs r cs 120mv v rmsmax ?? 2p omax ? ------------------------------------------------------------- > (eq. 4) p rcs i rmsmax () 2 r cs ? = (eq. 5) figure 12. typical pfc input filter circuit figure 13. low cost pfc input filter circuit table 2. c f1 po < 100w 100w < po < 500w po > 500w typical c(f)/100w 0.68 0.33 0.22 c f1 c f2 v line c f3 emi choke l m bridge recfifier l f c f1 c f2 v line c f3 emi choke l m bridge recfifier l f http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 12 fn8258.0 february 26, 2013 harmonic distortion minimum, it is desirable to set the control bandwidth much lower than twice of the line frequency. the recommended voltage loop bandwidth is 10hz. during start-up, the compensation capacitors and the charging current from the error amplifier sets the input power increase rate. thus, soft-start is achieved. the comp is discharged during shutdown and fault conditions. light load efficiency enhancement for pc, adaptor and tv applications, it is desirable to achieve high efficiency at light load conditions and low standby current. the isl6730a, isl6730b, isl673 0c, ISL6730D can enter light load efficiency mode automatically. the voltage error amplifier output, comp, is an indicator of the average input power level. the controller compares the v(comp) and v(skip). if v(comp)-1v is less than v(skip)*0.25, the pfc controller stops gate switching and the comp pin voltage is clamped to v(skip)+0.6v. isl6730a/c use a fixed v(skip), which is 1.4v; for isl6730b/d, the skip function are disabled. the controller exits skip mode when v fb drops to 88% (typical) of the reference voltage or when the sensed returned current exceeds 29a. protection circuits input brownout, bo protection brownout occurs when there is a drop in the line voltage. the bo pin is a dual function pin. the bo pin detects the brownout condition and shuts down the gate driver and controller. during normal operation, the bo pin is used to compensate the effect of the input line voltage change on the voltage loop. to keep the harmonic distortion low, the corner frequency formed by the r bo and c bo should be lower than 6hz. the bo pin is the output of the average voltage of the rectified voltage. the pfc controller is turned off when the bo pin drops below 0.4v. this protects the pfc power stage to enable operation at or below brownout condition for long periods of time. the controller resumes oper ation when the bo pin returns to 0.5v. the bo pin is usually connected to gnd through a capacitor, c bo . to avoid distortion on the vin pin, select c bo so that: overcurrent protection the peak current limiting function prevents the inductor from saturation. the gate driver turns off when the current goes above the current limit. overpower protection the overpower protection is implemented by limiting the comp pin voltage higher than 3.85v (typical). overvoltage protection if the voltage on the fb pin exceeds the reference voltage by about 4%, the gate driver is turned of f. the controller resumes normal operation after the fb pin drops below reference voltage. over-temperature protection the isl6730a, isl6730b, isl6730c, ISL6730D is protected against over-temperature conditions. when the junction temperature exceeds +160c, the pwm shuts down. normal operation is resumed when the junction temperature decreases below +135c. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 14 shows the critical power components; q 1 , d and c out . to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of the ground or the power plane in a printed circuit board. the components shown in figure 14 should be located as cl ose together as possible. please note that the capacitors c vcc and c o each represent numerous physical capacitors. locate the isl6730a, isl6730b, isl6730c, ISL6730D within 2 inches of the mosfet, q 1 . the circuit traces for the mosfets? gate and source connections from the isl6730a, isl6730b, isl6730c, ISL6730D must be sized to handle up to 1.5a peak current. component selection guidelines a 300w, universal input, pfc converter design is provided for demonstration. the design method is for a continuous current mode power factor correction boost converter with the isl6730b/d. the switchin g frequency is 62khz. c bo 0.22 f ? (eq. 6) figure 14. critical current power components q 1 c out l d gate vcc c vcc http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 13 fn8258.0 february 26, 2013 table 3 shows the design parameters. boost inductor selection first, calculate the maximum input rms current, i inmax. where is the converter efficiency at v rmsmin . pf is the power factor at v rmsmin. assuming the current is sinusoidal and the peak to peak ripple at line is 40%. the boost inductor, l bst , is given by the following equation: the peak current of the inductor is the sum of the average peak inductor current and half of the peak to peak ripple current. select and design the boost inductor as given by equation 11. the isl6730a, isl6730b, isl6730c, ISL6730D provides peak current limit function that can prevent the boost inductor saturation. assuming 25% margin is given to the ocp threshold, select and design the boost indu ctor with saturation current given by equation 11 with 25% more. input rectifier the maximum average input current is calculated: select the bridge diode using equation 15 and sufficient reverse breakdown voltage. assuming the forward voltage, v f,br , is 1v across each rectifier diode. the power loss of the rectifier bridge can be calculated: input capacitor selection refer to table 2 for the recommend ed input filter capacitor value. this is the recommended capacitor used after the diode bridge. for better power factor, less capacitance can be used. to lower the input filter inductor size, more capacitance can be used. two 0.47f capacitors in parallel are used for c in . boost diode selection the boost diode loss is determined by the diode forward voltage drop, v f and the output average current. the maximum output current is: the forward power loss on the diode is: the idd03e60 part is selected. the reverse recovery loss on the diode can be calculated. the q rr is found from the diode datasheet. q rr = 220nc when i f =3.5a. the reverse recover loss on the diode can be estimated: the total power loss on the diode is: mosfet power dissipation the power dissipation on the mosfet is from two different types of losses; the condition loss and the switching loss. for the mosfet, the worst case is at minimum line input voltage. first, the drain to source rms current is calculated: table 3. converter design parameters parameter conditions min typ max unit vline 85 115 265 vac fline 47 63 hz p omax maximum output power 300 w t hold hold up time 20 ms efficiency vline = 115vac 92 % i inmax p omax v ? rmsmin ----------------------------------- = (eq. 7 i inmax 300w 0.92 85v ? ---------------------------- 3.84a == (eq. 8) l bst 2v rmsmin 0.4 f sw 2 ? ? i inmax ? --------------------------------------------------------------- - 1 2v rmsmin ? v out --------------------------------------- ? ?? ?? ?? ? (eq. 9) l bst 85v 0.4 62khz 3.88 ? a ? ----------------------------------------------------- - 1 285v ? 390v ----------------------- - ? ?? ?? ? 617 h = (eq. 10) i lpeak 2i ? inmax 1 0.4 2 ------- - + ?? ?? ? = (eq. 11) i lpeak 23.88a ? 1 0.4 2 ------- - + ?? ?? ? 6.5a == (eq. 12) i inave max () 22 ? i inmax ? ------------------------------------------ = (eq. 13) i inave max () 22 ? 3.88a ? -------------------------------------- 3.5a == (eq. 14) p br 2v fbr , ? i inave max () ? = (eq. 15) p br 21v ? 3.5a ? 7w == (eq. 16) c in 300w 0.33 100 ----------- ? 0.99 f == (eq. 17) i out max () p omax v out -------------------- = (eq. 18) i out max () 300w 390v --------------- - 0.77a == (eq. 19) p fd i out max () v f ? = (eq. 20) p fd 0.77a 1.85v ? 1.42w == (eq. 21) p rrd 1 4 -- - q ? rr v out ? f ? sw = (eq. 22) p rrd 1 4 -- - 220nc ? 390v ? 62khz ? 1.33w == (eq. 23) p d p fd p rrd + 1.42 1.35 + () w2.75w == = (eq. 24) i ds max () i inmax 1 82 3 ---------- - v rmsmin v out ------------------------- - ? ? = (eq. 25) i ds max () 3.88a 1 82 3 ---------- - 85v 390v ------------- - ? ? 3.3a == (eq. 26) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 14 fn8258.0 february 26, 2013 the mosfet, spp20n60c3 is selected. the switching loss of the mosfet consists of three parts: the turn-on loss, the turn-off loss and the diode reverse recovery loss. from the mosfet datasheet, the typical switching losses curves are provided. when r g = 3.6 , i d = 6a, e on = 0.015mj, e off = 0.007mj. the switching loss due to transition is calculated: the diode reverse recovery incurs additional power loss on the mosfet. this loss can be estimated as: this loss is also related the di/dt during the mosfet turn-on. the di/dt can be found out from the mosfet datasheet. at r g = 3.6 , the turn-on di/dt is 4000a/s. from the typical reverse recovery charge curve at t j = +125c, the q rr = 220nc when i f = 3.5a. the total loss on the mosfet output capacitor selection the output capacitor, c out , is required to hold the output above 300v during one line cycle. for capacitors with 20% tolerance, the tolerance should be taken into consideration. thus, the output capacitance should be greater than: calculate the ripple rms current through the capacitor: select the proper capacitor according to the hold time and ripple rms current requirement. the actual capacitance is 270f. it is important to make sure th e output peak-to-peak ripple is less than the minimum ovp thre shold as specified in the ?electrical specifications? table on page 6. the esr at 2 times of the line frequency of the capacitor is found in the capacitor datasheet. the esr of the output capacitor is 770m at 100hz. the minimum ovp threshold is 103% of the nominal output value. the maximum output peak to peak ripple should be less than 6% of the nominal value, which is 23.4v p-p . current sensing resistors please refer to equation 4 for calculation of the current sensing resistor r cs . while a large r cs renders better current sensing accuracy, larger r cs also incurs higher power dissipation. select r cs from available standard value resistors to determine the sense resistor. the maximum power dissipation on the r cs occurs at low line and full load condition. the maximum power dissipation is calculated: the resistor, r sen sets the overcurrent protection limit. from equation 3, r sen should be greater than: where |x| stands for the abs(x) function. select r sen from available standard value resistors, the selected r sen is 3.16k . current loop compensation the input current shaping is achieved by comparing the sensed current signal to the sensed input voltage signal. the current error amplifier (gmi), together with the current compensation network, adjusts the duty cycle so that the inductor current traces the sensed rectified voltage. thus, unity power factor is achieved. the compensation network consists of the trans-conductance error amplifier (gmi) and the impedance network (z icomp). the goal of the compensation networ k is to provide a closed loop transfer function with the suff icient 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the open loop phase at f 0db and 180. the following equations relate the compensation network?s poles, zeros and gain to the components (r ic , c ic and c ip ) in figure 15. p cond i ds max () 2 r ds on () ? = (eq. 27) p cond 3.3a 2 0.3 ? 3.27w == (eq. 28) p sw e on e off + () f ? sw = (eq. 29) p sw 0.015mj 0.007mj + () 62khz ? 1.36w == (eq. 30) p rr q rr v out ? f ? sw = (eq. 31) p rr 220nc 390v 62 ? khz ? 5.32w == (eq. 32) p cond p sw p + rr + 3.27w 1.36w 5.32w ++ 9.95w == (eq. 33) c out 2t hold p ?? omax v out 2 v hold 2 ? ---------------------------------------------------- 10.2 + () ? (eq. 34) c out 2 20ms 300w ?? 390 () 2 300v () 2 ? ---------------------------------------------- 10.2 + () 232 f = ? (eq. 35) i corms max () i out max () 82 3 ---------- - v out v rmsmin ------------------------- - ? 1 ? = (eq. 36) i corms max () 0.77a 82 3 ---------- - 390v 85v ------------- - ? 1 ? 1.633a == (eq. 37) v opp i out max () 2 f line c out esr ?? () 2 1 + 2 f line () c out 0.8 ?? ------------------------------------------------------------------------------ - ? = (eq. 38) v opp 0.77a 2 100hz 270 f0.77 ??? () 2 1 + 2 100hz ? () 270 f0.8 ?? ----------------------------------------------------------------------------------------------- ? 6.6v == (eq. 39) r cs 120mv 265v 0.92 ?? 2300w ? ------------------------------------------------------ - 0.069 = (eq. 40) r cs 0.068 = (eq. 41) p rcsmax i inmax 2 r ? cs = (eq. 42) p rcsmax 3.88a 2 0.068 ? 1.023w == (eq. 43) r sen r cs i lpeak 10.25 + () ? ? 20.5i oc ? ------------------------------------------------------------------- - (eq. 44) r sen 0.068 6.6a 1.25 ? ? 20.18ma ? ------------------------------------------------------- - 3.117k = (eq. 45) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 15 fn8258.0 february 26, 2013 use the following guidelines for locating the poles and zeros of the compensation network. the cross over frequency of the current loop should be set between 2khz to 100khz. at cross over frequency, the transfer function from duty cycle to inductor current is well approximated by equation 48: it is recommended to set the cross over frequency from 1/10 to 1/6 of the switching frequency wi th phase margin of 60. a high frequency pole is set at 1/2 of the switching frequency for ripple filtering. in this example, we set the cross over, f c at 1/6 of the switching frequency. where f c = f s /6 = 10.3khz, m is the phase margin, which is 60. f p = f s /2 = 31khz. thus, the current loop compensation zero is: the total compensation capacitance is calculated: the value of the noise filtering capacitor is: the value of c ic is: the value of r ic is: select the r c value from the standard value, we have: r ic = 4.02k , c ic = 18nf, c ip = 1.2nf. figure 17 shows the actual bode plot of current loop gain. figure 15. inductor current sensing scheme q 1 c out v out l c f1 r cs isen r sen current mirror 2:1 i cs icomp i ref gmi r ic c ic r is c ip v i 80 40 20 0 -20 -40 -60 -80 -100 f p 100k 10k 1k 100 from duty to f z compensation gain (db) frequency (hz) gain modulator gain current gain open loop gain figure 16. asymptotic bode plot of current loop gain inductor current f z 1 2 r ic c ? ic ? ----------------------------------- - = (eq. 46) f p 1 2 r ic c ip c ? ic c ip c ic + ----------------------- - ? ? --------------------------------------------------- = (eq. 47) g id s () v out l bst s ? --------------------- - = (eq. 48) f z f c f c f p ------- ?? ?? ?? atan m + ?? ?? ?? tan -------------------------------------------------------- = (eq. 49) f z 62khz () 6 ? 2 6 -- - ?? ?? atan 60deg + ?? ?? tan ------------------------------------------------------------ - = 2.12khz = (eq. 50) c ip c ic v out l bst 2 f c () 2 ? -------------------------------------- - a idc v m ------------- r cs r sen --------------- - ?? ?? ?? ?? 1f c f z ? () 2 + 1f c f p ? () 2 + ------------------------------ - ? ?? ?? ?? ?? = + (eq. 51) c ip c ic 19.8 () nf = + (eq. 52) c ip c ip c ic + () f z f p ---- = (eq. 53) c ip 14.9nf 2.12khz 31khz ---------------------- - ? 1.35nf == (eq. 54) c ic 19.8nf 1.35nf ? 18.4nf == (eq. 55) r ic 1 2 2.12khz 18.4nf ?? ---------------------------------------------------------- - 4.11k == (eq. 56) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 16 fn8258.0 february 26, 2013 input voltage setting first, set the bo resistor divider gain, k bo according to equation 1 and equation 2. assuming the converter starts at v line = 80v rms , then the bo resistor divider gain, k bo should be: in this design, two 3.3m ? resistors in series are used for r in2 . so, r in1 is calculated: using resistor from the standard value, r in1 = 43k ? , the actual k bo is calculated: negative input capacitor generation the isl6730a, isl6730b, isl673 0c, ISL6730D generates an equivalent negative capacitance at the input to cancel the input filter capacitance. thus, more input capacitors can be used without reducing the power factor. the input equivalent negative capacitance is a function of the current sensing gain, bo resistor divider gain and the compensation components. this equivalent negative capa citor cancels the input filter capacitor required for emi filtering. therefore, the displacement power factor significantly improves. for example, c f1 = 0.68f, c in = 0.94f, using the low cost emi filter shown in figure 13. when v line = 230vac, f line = 50hz, p o = 60w. assuming 95% efficiency under the above test condition, the resistive component, which is in phase to voltage: the reactive current through the input capacitors: thus, the displacement power factor is: the reactive current generated by the equivalent negative capacitor is: with the equivalent negative capacitor, the total reactive current reduces to: the displacement power factor increases to: voltage loop compensation the average diode forward curr ent can be approximated by: assuming the input current traces the input voltage perfectly. the input power is in proportion to (v comp - 1v). where comp is the v comp - 1v. 1v is the offset voltage. r is is the internal current scaling resistor. r is = 16k . figure 17. bode plot of the actual current loop gain -20 0 20 40 60 80 gain (db) 10 100 1x10 3 0 45 90 135 180 frequency (hz) phase () 45 60 10.5khz 1x10 3 1x10 3 10.5khz k bo 0.5v 80v 2v ? ------------------------ 0.00641 == (eq. 57) r in1 0.00641 1 0.00641 ? ------------------------------ - 6.6m () ? 42.6k == (eq. 58) k bo r in1 r in1 r in2 + -------------------------------- - 0.00647 == (eq. 59) c neg k bo 0.8 v m v out --------------- - ? ? ?? ?? ?? r sen r cs a idc ------------------------- - c ic c ip + () = (eq. 60) c neg 0.00647 0.8 1.5 390 --------- - ? ? ?? ?? 3.16k 0.068 1.9 ? --------------------------- 18nf 1.2nf + () = 0.62 f = (eq. 61) i a p o v line 0.95 ? -------------------------------- - = 0.275a = (eq. 62) i c v line 2 f line ? () ? c f1 c in + () ? = 0.117a = (eq. 63) pf dis i a i a () 2 i c () 2 + ----------------------------------- = 0.92 = (eq. 64) i cneg v line 2 f line ? () ? c neg () ? = 0.045a = (eq. 65) i c i cneg ? 0.072a = (eq. 66) pf dis i a i a () 2 i c i cneg ? () 2 + ------------------------------------------------------- - = 0.967 = (eq. 67) i dave () p in v out --------------- - = (eq. 68) i dave () r sen r cs 0.5 r ? is ? --------------------------------------- 1 v out --------------- - ? 0.25 22 () ? () 2 k bo ? ----------------------------------------------- - ?? ?? ?? ?? comp ? ? = (eq. 69) i dave () 0.598 a v --- - comp ? = (eq. 70) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 17 fn8258.0 february 26, 2013 thus, the transfer function from v comp to v out is: as shown in figure 18, the voltage loop gain is: the output feedback resistor divider gain, g div is: the compensation gain uses external impedance networks as shown in figure 18, z comp (s) is given by: the targeted cross over frequency, f cv is 8hz. the high frequency pole, f pv is required in order to reject the 2 time line frequency component. f pv = 20hz. the targeted phase margin is 60. the zero, f zv is calculated: then the total capacitance used for compensation is calculated: thus, the total compensation capacitance is: choose components from the standard values. we have c vp = 100nf, c vc = 1500nf, r vc = 82.5k ? . the actual bode plot is shown in figure 20. fb comp gmv i fb 2.5v r fb1 r fb2 vout figure 18. output voltage sensing and compensation rvc cvc cvp g ps s () v out s () comp ----------------------- - = 1 c o s ? --------------- - i dave () comp -------------------- ? = (eq. 71) g ps s () i dave () c o s ? ------------------- 1 comp -------------------- ? ?? ?? ?? = 0.598 c o s ? --------------- - = (eq. 72) g vloop s () g ps s () g div gmv z comp ? ? ? s () = (eq. 73) g div v ref v out --------------- - = (eq. 74) z comp s () 1 c vc c vp + () s ? -------------------------------------- - r vc c vc s1 + ? ? r vc c vc ? c vp ? c vc c vp + ----------------------------------------- - s ? 1 + ------------------------------------------------------------ - ? = (eq. 75) 100 80 60 40 20 0 -20 -40 -60 f pv 1k 100 10 1 f zv gain (db) frequency (hz) figure 19. asymptotic bode plot of current loop gain f cv g ps (s) z comp (s) g vloop (s) gmv*gdiv f zv f cv m f cv f pv () ? () atan + () tan ----------------------------------------------------------------------------- - = (eq. 76) f zv 8hz 60deg 8hz () 20hz () ? () atan + () tan ------------------------------------------------------------------------------------------------ 1.15hz == (eq. 77) c vc c vp + g ps i2 f cv () ? () g div gmv ? ? 2 f cv () ------------------------------------------------------------------------------------------ - f cv f zv ? () 2 1 + f cv f pv ? () 2 1 + -------------------------------------------- ? = (eq. 78) c vc c vp + 1829nf = (eq. 79) c vp 1829nf f zv f zp ---------- - ? 105nf == (eq. 80) c vc 1829nf 105nf ? 1724nf == (eq. 81) r vc 1 2 f zv c vc ?? ? ------------------------------------------ - 81.2k == (eq. 82) figure 20. bode plot of the actual voltage loop gain -40 -20 0 20 40 60 gain (db) 0 1 10 100 1x10 3 0 15 30 45 60 75 90 frequency (hz) phase (deg) http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8258.0 february 26, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet : isl6730a . to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change february 26, 2013 fn8258.0 initial release http://www..net/ datasheet pdf - http://www..net/
isl6730a, isl6730b, is l6730c, ISL6730D 19 fn8258.0 february 26, 2013 package outline drawing m10.118 10 lead mini small outline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m http://www..net/ datasheet pdf - http://www..net/

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